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RobShepherd's avatar
RobShepherd
Icon for New Contributor rankNew Contributor
4 years ago
Solved

AVALON IP LIBRARY

Hello, I am investigating the AVALON Bus Protocol as a standard to be used in a RISC-V SoC design. I understand AVALON to be an OPEN standard but wish to understand what AVALON IP/Macros/RTL are a...
RobShepherd's avatar
RobShepherd
Icon for New Contributor rankNew Contributor
4 years ago

Hello again,

(Sorry to ask)

Do you know whether the IP that is described in the guide is available in HDL form or is it a drag and drop thing that is configured and pops out from the Quartus process as a binary for programming FPGA.

The guide is named "Embedded" IP which may mean the IP is embedded in the tool only but section 41.3 (item suggests a "Generate HDL" stage but I am not sure if this applies to all items in the guide.

Please let me know if you have experience of this.

Thank you,

Rob

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    Yes, you can drag and drop and edit the IP as per the guide, and after you connect everything without any warnings/errors, you can generate the HDL.