Avalon Interconnect Dynamic Bus Sizing and Bursts

Unfortunately I am not the creator of this testbench. And it will be hard for the modification as it will take efforts on this.

I have another design that demonstrate different width work but it is different than your design. This design uses on chip ram as the slave. It successfully accept the burst when the width data is narrower at the slave side, the read is correct as well.

You can take a look on this,

What you need to do is to follow the steps below:

cd to directory ... /altera_avalon_bfm_master/hdl/avalon_bfm_master/scripts/qsys_system/simulation/mentor/

1) source msim_setup.tcl

2) com

3) vlog -sv qsys_system_tb.sv -L altera_common_sv_packages

4) elab +nowarnTFMPC

5) do qsys_system_tb.do

6) run -a

Look into the test_number 4 in the modelsim simulation, you will find it it is working.

Attached the screenshot as well as the zip files.