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sadad's avatar
sadad
Icon for New Contributor rankNew Contributor
6 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago
It will take me some time to rewrite the testbench. Not sure if you can wait for this?
  • BInos's avatar
    BInos
    Icon for New Contributor rankNew Contributor
    6 years ago

    are you the creator of this testbench?

    yes it would be fine.

    But my main goal is not an fully automated testbench which tests latencies / cornercases.

    My main goal is to get burst read transfers working when adapting from 32bit to 8bit avalon.

    Or do i have to try it out without bfms in real hardware