Forum Discussion

AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Avalon -MM Intel Stratix 10 Hard IP+ for PCI Express

Hi, i'm trying to use the Avalon -MM Intel Stratix 10 Hard IP+ for PCI Express for my FPGA application but the use guide doesn't provide me enough informations for my level of knowledge. Is there an...
AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I forgot to say that in the RX module, i send the data to the host everytime the memory is not empty. So if there is data in memory, a process will fetch it from the memory and sends it to the host.

In the TX part, if the memory is not full, a process will allow the reception of data from the host at the memory location specified by the TX module (not specified by the host).