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NZhan1's avatar
NZhan1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Arria10 DMA失败

使用10AX027和CPU调试PCIe时发现以下问题： 调试过程中软件驱动负责分配一块物理内存，然后把物理内存地址写入FPGA，FPGA从这个物理内存地址做DMA，读取内容。 在Xeon系列的硬件平台上的异常现象是： 当驱动分配的物理内存在4G以上时，FPGA做DMA是可以的，分配到4G以下时，FPGA发送tlp的读请求后，始终得不到响应，DMA失败。 做了以下尝试：​ 将FPGA及...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

If the read request is sent out from the AVST to DMA. At this point, the PCIe IP still working fine. Do you mean the AVST interface does not receive the completion from the custom DMA? If yes, then this is required to debug from the DMA perspective.

Regards -SK

  • NZhan1's avatar
    NZhan1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago
    Hi SK， The read request is sent out from the DMA to AVST and then TX channels, and finally the CPU. But DMA didn’t receive the completion from the CPU. We will make sure that AVST can receive completion by signaltap first. It there any similar situation occurs on others’ Arria10 and Xeon CPU plartform before? Regards， Nicole