Forum Discussion

qiaomeng's avatar
qiaomeng
Icon for New Contributor rankNew Contributor
4 years ago

Arria 10

Why is the locked output of my iopll phase-locked loop not pulled high, but I want to get a 10M pll output clock, the actual test only generates 5M, what could be the problem, my FPGA is Arria10？plea...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Check the signal integrity of the input clock. Is it differential? If yes, do you have proper termination? Are the voltage supplies stable?

Check the Pin Connection Guidelines of the device.

Regards