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TerryU's avatar
TerryU
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7 years ago

Arria 10 Transceiver PHY parameters for CDR

Hi experts, I have reference lock issue on high speed interface mode. Then, I would need CDR-PLL related values, actually I have found some improvement with modification. However the following param...
TerryU's avatar
TerryU
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7 years ago

Additionally, I think those parameters are PLL-VCO analog character settings judging from parameter names, so I think any modification for them would not affect any logical process for Transceiver communication process. And this issue would be issue on analog area. Anarolg-reset will not affect, as Fine board is always fine and Fail board is always fail even on any timing or no analog reset. I think, rx_analogreset affects to PMA process only.

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Thanks,

TerryU/Tetsuya