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CHebl's avatar
CHebl
Icon for New Contributor rankNew Contributor
6 years ago

Arria 10 Device Specifications

I want to dynamically reconfigure the line rate of my transceivers on an Arria 10 FPGA. When looking at the register map of the ATX PLL I noticed the configuration capabilities for the LC-tanks and l...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
HI, What you are looking for is the ATX PLL internal spec that's not available in FPGA datasheet doc. Intel FPGA recommendation to customer is to use the auto mode to let Quartus auto configure the ATX PLL optimal setting for user rather than let user manually tweak the setting themself. Thanks. Regards, dlim