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KCMurphy's avatar
KCMurphy
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Apparent bug in LPDDR3 simulation (altera_emif:19.2.0) Arria 10

During a long burst read from a (simulated) Micron LPDDR3 memory, the simulation of the Intel Arria 10 hard controller (quarter-rate) eventually drops a 32-bit word (it delivers xxx's for that portio...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi KCMurphy,


    The emif_usr_clk is around 199MHz and that is in the acceptable range.

    The ref_clk is still at the 200MHz.


KCMurphy's avatar
KCMurphy
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Except that it does not proceed normally, as I have documented.

First, answer this: after calibration, what period or frequency do you see on emif_usr_clk ?

This is the quarter-rate timing to the user logic and is supposed to be exactly 1/4 of the 800MHz DDR bus clock.