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KCMurphy's avatar
KCMurphy
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Apparent bug in LPDDR3 simulation (altera_emif:19.2.0) Arria 10

During a long burst read from a (simulated) Micron LPDDR3 memory, the simulation of the Intel Arria 10 hard controller (quarter-rate) eventually drops a 32-bit word (it delivers xxx's for that portio...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi KCMurphy,


    The emif_usr_clk is around 199MHz and that is in the acceptable range.

    The ref_clk is still at the 200MHz.


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi KCMurphy,


Thank you for sharing the design.

I have run the simulation by using Questasim and the design has passed the calibration.

Usually the design that passed the calibration will work normally.

8 long-words will be equal to 256 bits which is the maximum width of the read and write data conduit.

Any data that exceed the limit will be invalid.


Let me know if you have different thought on this.

Thanks.