Forum Discussion
JET60200
Contributor
ContributorAN829 - PCIe BAR[2] to read/write FPGA-EMIF-DDR4 over 1GB area
hello ,
[ Scenario] We can run AN829 PCIE driver on Arria10 EVM Board.
In the FPGA design example, [pcie_a10_hip] -> [rxm_bar2] can read/write to [ FPGA Emif -> ctrl_amm Slave Node] where we h...
I forgot to explain further. In AN829, DDR4 is connected to PCIe DMA port which means DDR4 can only be accessed via DMA control only.
That's why I suggested you to switch to use PCIe IP without enabling the DMA logic insides the IP. Then user can connect PCIe IP directly to memory (like DDR4) and access it.
Thanks.
Regards,
dlim
Deshi_Intel
Regular Contributor
Regular ContributorHI,
It doesn't work like that. You are looking at example design that use (PCIe + DMA) IP.
If you just want to use PCIe IP that interact with memory directly, then pls consider to check out below example design that use (PCIe) only, no DMA
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avmm.pdf
- This is the example design that you can generate from PCIe IP directly
- This example design currently connect to on chip RAM but you can replaced with DDR4 if you want
Thanks.
Regards,
dlim
