AN744 Arria10 - IEEE1588 Design

Thnaks! So, probably should be better to redesign own application... (!). I'm attemp to understand AN744. IEEE1588 is applied directly to ToDs: no physical clock modification are made. On this design, there is one Master Tod, and it seems distribute own sync directly to both channels 0,1. Reading about IEEE1588, an Ordinary Clock Master shold give it's syncro to Ordinary Slave via Ethernet , sending PTP messages with related timestamps, but this design seems concepted differently.... There is any possibility to obtain more infos? Thanks again for any support!