Forum Discussion
mbandala
New Contributor
New ContributorAN 729: JESD204B IP Reference Design
I am currently trying out this example with a slight modification required for my hardware setup. I am using an Arria 10 10AS027H4F34I3SG DEVICE. I have both a USB Blaster II and an Ethernet Blaster ...
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi Michael,
The free Intel® FPGA IP Evaluation Mode allows you to evaluate the licensed Intel® FPGA IP cores in simulation and hardware before purchase. You can generate time limited programming files (<project name>_time_limited.sof) that expires at the time limit.
Please refer this JESD204B Intel® FPGA IP Evaluation Mode User Guide
All the Best !!
Kshitij Goel
