Forum Discussion
New ContributorALTPLL Error: Clock Input port of PLL must be driven by non-inverted input pin or another PLL.
Hello, Sorry for delay , I caught into another stuff,
Today morning i get chance to look at your design files , Here is changes i did which made it work
i) Add wire clk_200MHz (which is missing in your top module )
ii) removed th /*synthesis keep */ in clk_int. After these changes it is working for me.
One more thing i noticed is , LVDS IP is opted for internal clock and input of the clock is feed from PLL. iam not sure why ..but i can say it is going to take more PLL resources
Let me know if you have any question /concern ?
Thank you ,
Regards,
Sree
New ContributorI have tried the solution suggested in KDB article shared above. I couldn't find the command assigning blackbox to any level of hierarchy, still I added the suggested command, but the error persists. I have also tried adding multiple PLL clock inputs, that too does not effect this error.
