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SMS's avatar
SMS
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7 years ago
Solved

ALTPLL Error: Clock Input port of PLL must be driven by non-inverted input pin or another PLL.

Device: Max10 (10M16SAE144I7G) I am trying to use the ALTPLL IP core in my design for frequency synthesis. The clock input of the ALTPLL is directly fed by external oscillator via one of the dedicat...
  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    7 years ago

    Hello, Sorry for delay , I caught into another stuff,

    Today morning i get chance to look at your design files , Here is changes i did which made it work

    i) Add wire clk_200MHz (which is missing in your top module )

    ii) removed th /*synthesis keep */ in clk_int. After these changes it is working for me.

    One more thing i noticed is , LVDS IP is opted for internal clock and input of the clock is feed from PLL. iam not sure why ..but i can say it is going to take more PLL resources

    Let me know if you have any question /concern ?

    Thank you ,

    Regards,

    Sree

SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hello , Can you let me know in which pin exactly clock is connected ? from the error it is very clear that clock is connected to the inverted pin which is name_N. If the clock input to the FPGA is single ended it must need to connect to the pin_P (non-inverted ). Also if you still facing the issue , can you also try below constraint https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd02012010_744.html?_ga=2.211051409.504554538.1557376570-1310395169.1552995784&erpm_id=8221258 Thank you , Regards, Sree