Honored Contributor
Honored ContributorWell, I didn't quite understand what you meant by:
"edit the top level ddr file and manually instantiate the additional alt_ddio blocks" Mainly I didn't understand it since I didn't think it would work. It seems this method wouldn't work because the additional instantiation of the alt_ddio at the top-level wouldn't have the inputs needed to replicate the original instance. If I assumed that you meant bottom level instead of top level ddr file, I altered ddr2_sodimm_phy_alt_mem.v, and the ports connecting to the top level. In this style, I added generate statements to instantiate multiple ddr2_sodimm_phy_alt_mem_phy_ac to replicate the outputs. Actually full disclosure, I did it for the mem_we_n first since it seemed simpler than for the change for the mem_ba (bank address) that I originally asked about. But, I now see that the change for mem_ba should be about the same, specifically, generate multiple instances and add a new output to each module in the hierarchy for each instance, instead of changing the bus width as I did for mem_we_n. Thank you
