Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAltera Generic Tri-state Controller optimization for ZBT SRAM
Hello, i'm using EP4CGX150DF31 on custom PCB with dual Cypress NoBL (= Zero Bus Turnaround) SSRAM CY7C1463AV33. Theoretical Bandwidth 32 bits x 65 MHZ (memclk speed) = 2080 Mbit/s QSYS SRAM i...
Altera_ForumHonored Contributor
Honored ContributorHello again.
I've find optimum parameters for Cypress ZBT SRAM. Maybe it can be usefull for anyone else. Read wait time: 0 Wite wait time: 0 Setup time: 0 Data Hold Time: 0 Maximum pending data transactions: 64 Turnaround time: 0 Timing units: Cycles Read latency: 3 Chipselect through read latency is unchecked Full preset for Generic Tri-state controller in attachment And else I had to instatiate PLL and shift 65 MHZ clock which drive SRAM's CLK pin to -3.07 ns. All other logic driven by not shifted clock. New SignalTap images of Read/Write operation: https://www.alteraforum.com/forum/attachment.php?attachmentid=8439 https://www.alteraforum.com/forum/attachment.php?attachmentid=8440 https://www.alteraforum.com/forum/attachment.php?attachmentid=8441 Good luck
