Forum Discussion
Agilex 5 GTS PMA/FEC Direct Loopback
- 1 year ago
Hi,
Thanks for your update.
Based on your description, it seems your datapath is structured as follows:
Oscillator → tx_parallel_data input → GTS PHY → rx_parallel_data output → DMA → HPS
To achieve this setup, you can enable the Parallel Loopback path (Path B). This configuration allows the parallel data fed into the TX interface to be directly routed to the RX interface, bypassing the serializer, deserializer, and CDR blocks.
This approach should help simplify your testing or validation process without involving the full high-speed serial path.
Let me know if you need further clarification or assistance.
Best regards,
Chee Pin
Hi,
I noticed that there seems to be some issue with the image uploading. Just to clarify, I am referring to the PMA-transmitter-to-receiver parallel loopback (TX2RXPAR) as in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs -> "Figure 21. PMA Loopback Modes". Sorry for the inconvenience.
- CheepinC_altera1 year ago
Regular Contributor
Hi,
Just following up to check if you have any further inquiries related to this topic that I can assist with. If everything has been addressed, I’m planning to close the case shortly.
Please feel free to let me know if there's anything else you'd like to discuss. Thank you!