Agilex 5 GTS PMA/FEC Direct Loopback

Hi,

Thanks for your update.

Based on your description, it seems your datapath is structured as follows:

Oscillator → tx_parallel_data input → GTS PHY → rx_parallel_data output → DMA → HPS

To achieve this setup, you can enable the Parallel Loopback path (Path B). This configuration allows the parallel data fed into the TX interface to be directly routed to the RX interface, bypassing the serializer, deserializer, and CDR blocks.

This approach should help simplify your testing or validation process without involving the full high-speed serial path.

Let me know if you need further clarification or assistance.

Best regards,

Chee Pin