adding altera vip to existing qsys design

Which clocks do you have inside your system?

I expect you have 74.25 MHz (720p) for the input and if you don't change the resolution, also for the output?!

So the Pixelclock is 74.25 MHz, but if you do not put the frequency up, you may loose information with your construction of CPS->FIR->CPS due to overflows/underflows.

To achieve a better result (in a first stage) you could insert another FrameBuffer to decouple everything. (Of course your frame rate with updated frames will go down).

So the pipeline could be:

CVI -> FrameBuffer -> CPS ->FIR -> CPS -> FrameBuffer -> CVO

The FrameBuffers should be configured with frame dropping and framerepetition.

In order to test the (I think it should be) underflow at the output you could also insert a trace system with a vip-monitor and put the underflow-output to a dedicated LED.

I hope this helps

Regards