adding 2 high speed reed solomon decoders increased the 'Logic Utilization' in 20% (only 7% was expected based on other project where i also added the same 2 high speed reed solomon decoders).

Hi,

As I understand it, you have some inquiries related to the logic utilization of the HS RS IP core in your design. For your information, you may then refer to the "Table 6. Performance and Resource Utilization for Stratix V Devices" in the High speed Reed solomon IP Core User Guide for the estimation of the resource utilization per HS RS IP core for your specific configuration.

As I compare the fit.summary reports for 5100 and 5101, I can observe differences between the resource utilization. Note that I notice that there seems to be differences between the number of XCVR channel use between the two design. To ease the comparison, I would like to recommend you to test with simple design ie with only 1 input and 1 output pin. Then compare the resource utilization with compilaton after adding one or two HS RS IP cores. You can then cross check with the Table 6 to see if there is any significant discrepancy.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin