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AINCE's avatar
AINCE
Icon for New Contributor rankNew Contributor
7 years ago

Accessing Cyclone V SOC I/O Pins for Boundary-Scan Testing

Hello, We have Cyclone V SOC FPGA (5CSEBA6U19I7SN) and we want to test HPS pins using Boundary-Scan Test. There is a warning in the 5CSEBA6U19_HPS.bsd file as shown in attached IMAGE1. The question ...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

sorry for very late response ;

I looked at the HPS bsd files , i believe the warning your are getting since hps files are using the hps jtag , but as i mentioned already you have to map hps pin to FPGA fabric and use the fpga bsd file .

Kindly let me know your thought on the same ?

Thank you,

Regards,

Sree