Forum Discussion

New Contributor

6 years ago

Accessing Cyclone V SOC I/O Pins for Boundary-Scan Testing

Hello, We have Cyclone V SOC FPGA (5CSEBA6U19I7SN) and we want to test HPS pins using Boundary-Scan Test. There is a warning in the 5CSEBA6U19_HPS.bsd file as shown in attached IMAGE1. The question ...

AINCE

New Contributor

6 years ago

Thank you for your reply,

In the attached .zip file, there are 3 bsdl files. Two of them are 5CSEBA6U19.bsd and 5CSEBA6U19_HPS.bsd and I downloaded them from the link below.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/bsdl/cyclone-v.html

5CSEBA6U19I7S_pre.bsd is generated from the Quartus II TCL Script tool.

BSDL_Files.zip28 KB

Forum Discussion

Accessing Cyclone V SOC I/O Pins for Boundary-Scan Testing

Recent Discussions

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models

F-Tile Ethernet Hard IP (100G)

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

Agilex-7 AXI MCDMA for PCIe hang