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AINCE's avatar
AINCE
Icon for New Contributor rankNew Contributor
7 years ago

Accessing Cyclone V SOC I/O Pins for Boundary-Scan Testing

Hello, We have Cyclone V SOC FPGA (5CSEBA6U19I7SN) and we want to test HPS pins using Boundary-Scan Test. There is a warning in the 5CSEBA6U19_HPS.bsd file as shown in attached IMAGE1. The question ...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Would it possible to share the bsdl file generated from the tcl console ? As of I read through the document looks it will support the hps pins via FPGA fabric.

Thank you,

Regards,

Sree