Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi Galfonz,
Thanks. - I am already having a design that communicates with x86 processor from NIOS II using the shared memory over the PCIe interface. - With new design my aim would be to reverse the shared memory and place it on the x86 processor DDR memory instead of FPGA SSRAM. - And aware of this would require some complex address translation logic to be included in the fabric.I am interested to know if someone has already achieved something similar and if it is possible to get hold of a reference design for this or related configuration to start with. Regards, Varun