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lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
5 years ago
Solved

About transceiver power-up calibration of arria 10

Hi sir, I am facing one confused problem about power-up calibration sequence of arria 10: From the transceiver section 7.3, It said that " If a system has an FPLL, an ATX PLL, and channels, ...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,


    As I understand it, you have some inquiries related to the calibration sequence for the A10 XCVR blocks. For your information, you should refer to the Figure 284 and Figure 286 for the calibration sequence which should be ATX -> fPLL -> PMA. There should be some typo at the initial description. Sorry for the inconvenience.


    Please let me know if there is any concern. Thank you.


CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.