About PCI Express generate a "Interrupt request" to Nios(Use DE2i-150)

Now I want to extend the project "pcie_fundamental" in system CD, but I meet some problems in software and Qsys part.

My target is generate a "interrupt" from PCIE at PC host, and deal with it in "nios ii for eclipse".

As shown in appendix "Qsys.JPG", I connect "PCIE Hard IP Compiler" and "Nios Processor" in IRQ(Interrupt request).

(If it has a connect error, please tell me.)

Qsys.JPG: https://drive.google.com/open?id=0b7gv38ouppiayupymfhrudbkavk

These are my questions:

1. How to generate a "interrupt request" from PCI Express to Nios?

2. Could I use below method to generate "Interrupt request"?

img1:https://drive.google.com/open?id=0b7gv38ouppiaoho3vzjkznbemle

img2:https://drive.google.com/open?id=0b7gv38ouppiaqvl6z2plmeledm8

img3:https://drive.google.com/open?id=0b7gv38ouppiarnbjewpkvgvaafe

Article mentioned that "Enables assertion of Avalon-MM interrupt CraIrq_o signal when the specified mailbox is written by the root complex".

How to enable "interrupt to Avalon MM", like this below(This C++ code in software part, and i try to enable P2A_MB_IRQ[0])?

(If it has a any error, please tell me.)

img:https://drive.google.com/open?id=0b7gv38ouppiar3rdmwlhlurlmmm

3. If above mentioned part is right, how to handle "Interrupt" when Nios II receive a IRQ(interrupt request queue)?

Could I register a ISR(Interrupt Service Routine) like below?

alt_irq_register(PCIE_HARD_IP_IRQ, 0, ISR);

Now I focus on What is PCI Express generate a interrupt request and Nios how to receive interrupt and how to handle it?

Appendixes "Qsys part" and "software part" can help you realize my question.

Qsys Part: https://drive.google.com/open?id=0b7gv38ouppiabkztvgztsdj3dza

Software Part: https://drive.google.com/open?id=0b7gv38ouppiaam12mg5ibkjhngs

(software part is use in PC host, not in use in "Nios II for Eclipse")

IP Compiler for PCI Express User Guide:

https://www.altera.com/content/dam/altera/www/global/en_us/pdfs/literature/ug/ug_pci_express.pdf (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_pci_express.pdf)

DE2i_150 FPGA System User Manual:

http://www.terasic.com.tw/cgi-bin/page/archive_download.pl?language=english&no=529&fid=c10b5ed89f1ec9f4b578f1407255b340

Sincerely yours, Williams