Forum Discussion
RamaMohan
Occasional Contributor
Occasional ContributorA10 PCIe SRIOV IP not sending completion to Root Port
We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completion...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi RamaMohan,
A quick check with you, could you please double check if this issue only happen in SRIOV variant but not the Avalon ST (without SRIOV) by using the third party BFM?
Regards -SK Lim
