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BJian12's avatar
BJian12
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6 years ago

A10 FPGA pcie一致性测试码型发送问题

在A10 FPGA的PCIE插卡上想使用PCIE Hard IP发送一致性测试码型，用于进行PCIE插卡的PCIE一致性测试。研究了一下文档。 发现在pcie的IP里面设置test_in[6]这个位为“1”是强制进入一致性测试模式。 查看代码发现IP对test_in这个输入信号例化的时候，例化为空（就是实际信号例化后面跟了一个空括号），但是根据文档里写的这个test_in默认是0x18...
BoonT_Intel's avatar
BoonT_Intel
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6 years ago

Hi By looking in the test_in table. Looks like you need to set the last 8 bits to 9'h188 (110001000). So the default value is correct.

For 1. Do you mean the txdetectrx loopback? This should happen automatically in the IP. You suppose can see this event from the ltssm state.