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yt_liu's avatar
yt_liu
Icon for New Contributor rankNew Contributor
5 years ago

A question about the clock signal of the CIC filter IP

Excuse me, I am testing the frequency response of the CIC filter IP using Quartus 19.1 Standard Edition and Arria V GX, and I have a question on the clock signal of the CIC filter IP core. I use the ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


It could be something related to the output rounding method, you may play around with that setting from the IP.


Regards -SK


yt_liu's avatar
yt_liu
Icon for New Contributor rankNew Contributor
5 years ago

Sorry for the late reply... I found out that I used a 1-bit PDM signal as the CIC filter's input but a signed signal should be at least 2 bits, and this caused the problem. Still thank you for your help! I think it may be better if the platform designer gives warning when the filter's input data width is set to 1 bit.