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assn1's avatar
assn1
Icon for New Contributor rankNew Contributor
3 years ago

a problems about using negative clk

The port definition is complete, but errors continue to occur. always @(negedge clk_1Msec or negedge rst) begin if(Control == 0) begin if(rst == 0) begin Msecs <= 0; Mins <= 0; Secs <= 0; Hou...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

This seem a syntax issue on if else condition for Verilog.

You need to check again the correct syntax.