125MHz PCIe application clock on a large cyclone V

This is getting silly.

I have to set "Limit interconnect pipeline" to 4 to get any latches in the main Avalon interconnect.

Even then they don't seem to appear in the right place. It is difficult to see where they are because all the lines are crossing at the point where the latches are added.

I'm feeding the BAR master into a simple non-pipelined 32bit avalon bridge that latches all the signals and issues a master read/write transfer two clocks later. By putting a 'false path' on the addresses (only latched once) I get past most the of the address related timing errors.

I've replaced some of the memory slaves with one that has an additional latch of the slave address (get rid of issues with setup time on WE).

But I've still got errors where (I think) waitrequest is looped back through the arbiter.

I've still got more stuff to add as well.