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Honored Contributor
Honored Contributor125MHz PCIe application clock on a large cyclone V
We are trying to get a large Avalon bus based design to pass timing using the 125MHz clock from the PCIe block. The design passed at 62.5MHz (just), but we want to use more than PCIe 1.0 x1 - whic...
Altera_ForumHonored Contributor
Honored ContributorI did try adding pipeline bridges, with more than 3 or 4 slaves per bridge it fails timing.
With that many bridges it is hard to see what is what. Once I get away from the PCIe BAR avalon master (which has deep levels of logic on it avalon outputs and waitrequest input) the problems seem to be associated with the address comparators and the slave arbiters generating waitrequest. I'm wondering whether asserting read/write a cycle after the address and giving a timequest a multi-cycle constraint on the address might help? Telling qsys to ad 1 cycle of additional latency just makes things worse! I'm not sure where it adds the latch, but it isn't anywhere near the right place.
