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Altera_Forum
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10 years ago

10g mac - avalon_st_tx_ready de-asserted in the middle of the packet transfer

Hi All,

Does anybody know why avalon_st_tx_ready de-asserted in the middle of the packet transfer?

Attached a capture of signal tap.

I can see a missing data on the pc that receive this packet. the missing data is correlated with data transmitted while avalon_st_tx_ready de-asserted.

Thanks

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    n Signal Tap : the packets are transmited by an external PC (was validate and works fine).

    In simuation : the same packets are transmited by a test bench.

    The fpga logic is ALTERA's IPs (MAC & PHY). no logic was added. Do you think altera has problem with this IP?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I think it's highly unlikely a problem with altera IP - ethernet cores are very mature.

    You could try raising a ticket with them

    Without you posting the design - there is little we can do to help.