100G E-tile error on Stratix 10 DX

I'm using 22.1. I have not been using 22.2 due to this issue: https://community.intel.com/t5/Intel-Quartus-Prime-Software/PCIe-HIP-clocking-regression-on-Stratix-10-MX-in-Quartus-Prime/m-p/1394323#M74234

The code that interfaces with the E-tile was developed from scratch based on the documentation for the Agilex F series part, and is used with minimal modification on the Stratix 10 DX. The core logic that does not interface with the E-tile was also written from scratch, but runs and builds correctly on many different FPGAs, including the Stratix 10 DX.

The problem is from the E-tile 100G Ethernet IP core.

I have not tried to build the example design, but I will give it a shot and see if I can replicate the issue. I suspect that maybe it has to do with some of the unused PTP signals being tied off, instead of being driven by registers.

Sure, the Stratix 10 DX and Agilex F are somewhat different, but the E-tile is ostensibly exactly the same on both. And the core logic already works fine on the Stratix 10 DX and 10G and 25G, only difference between 10G/25G/100G in terms of the core logic is clock frequency and datapath width. And the core logic runs correctly on many other FPGAs without any device-specific modifications (Xilinx Virtex 7, Xilinx UltraScale, Xilinx UltraScale+, Intel Stratix 10 MX, Intel Stratix 10 DX, Intel Agilex F).