Occasional Contributor
Regular ContributorHi Alex,
Apologize for late reply, as I am ooo for urgent.
I try to run your design, I am getting the same error.
I lay down some suggestion so that we can narrow down the issue.
As the architecture of Stratix 10 and Agilex F is quite different from hardware to software, we cannot guarantee the same design can completely work within both of them as a lot of factors need to be considered such as pin assignment, logic cells, I/O elements, IP, and IP cannot be migrated directly between different devices.
Regards,
Wincent_Intel
Occasional ContributorI'm using 22.1. I have not been using 22.2 due to this issue: https://community.intel.com/t5/Intel-Quartus-Prime-Software/PCIe-HIP-clocking-regression-on-Stratix-10-MX-in-Quartus-Prime/m-p/1394323#M74234
The code that interfaces with the E-tile was developed from scratch based on the documentation for the Agilex F series part, and is used with minimal modification on the Stratix 10 DX. The core logic that does not interface with the E-tile was also written from scratch, but runs and builds correctly on many different FPGAs, including the Stratix 10 DX.
The problem is from the E-tile 100G Ethernet IP core.
I have not tried to build the example design, but I will give it a shot and see if I can replicate the issue. I suspect that maybe it has to do with some of the unused PTP signals being tied off, instead of being driven by registers.
Sure, the Stratix 10 DX and Agilex F are somewhat different, but the E-tile is ostensibly exactly the same on both. And the core logic already works fine on the Stratix 10 DX and 10G and 25G, only difference between 10G/25G/100G in terms of the core logic is clock frequency and datapath width. And the core logic runs correctly on many other FPGAs without any device-specific modifications (Xilinx Virtex 7, Xilinx UltraScale, Xilinx UltraScale+, Intel Stratix 10 MX, Intel Stratix 10 DX, Intel Agilex F).
Regular ContributorHi Alex,
I am the same support engineer who works with you on the issue that happens in 22.2.
The escalation case was just assigned to debug engineer. Will continue to follow up on that.
You can try the suggested method of trying to replicate the issue.
As you mention that the design was built from scrap,
the possibility of missing some of the design elements might happen sometime/somewhere
Where it is quite hard to pinpoint, as the FPGA design somehow can be really complicated.
Meanwhile, I do suggest you try out the existing E-tite Ethernet Design for Stratix 10 Instead of modified form Agilex design,
Yes, you are correct by right there shall be the same for both as for E-tile
But, as the device is different, I do afraid there is a compatible issue with software, driver, system, kernel and other etc....
It is tested on our team and shall work fine.
Hope this help,
Regards,
Wincent_Intel
Regular ContributorHi Alex,
The clock will be obtainable in the new release of Quartus version 22.3.
Please try it in the newest version of the Quartus (once available).
This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
Best regards,
Wincent_Intel
