Forum Discussion

Occasional Contributor

3 years ago

100G E-tile error on Stratix 10 DX

I am attempting to build a design with an E-tile configured for 100G operation on a Stratix 10 DX device, and I am running in to some strange build issues. I am building designs for both Stratix 10 ...

Wincent_Altera

Regular Contributor

3 years ago

Hi,

Welcome to Intel Forum Support.

Could you share both the Quartus QAR for design with VQM and HDL source file for investigation?

Regards,

Wincent_C_Intel

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100G E-tile error on Stratix 10 DX

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