10/ 100 MII on Cyclone 10 GX

Hi Johnson, Your understanding of using 10/100 small MAC of TSE IP core is correct but Intel doesn't has reference design for 10/100 implementation. - You need to build your 10/100 design by yourself Or you can also leverage below TSE IP example design for ease of implementation. (Just ignore the 1000Mbps GMII function) Intel doesn't have example design for Cyclone 10 but we do have similar design for Arria 10. The FPGA is different but the TSE IP is the same. https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/arria-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design/ https://fpgacloud.intel.com/devstore/platform/17.1.0/Pro/arria-10-nios-ii-simple-socket-server-design-example/ Thanks. Regards, dlim