1-wire (onewire) SOPC builder component

i can not hand out the sources i wrote as the owner is the company i work for.

all you need from the maxim dallas verilog sources is the file onewiremaster.v

you need some avalon interface signals like

module SOPC_DS1Wire_Master (

// Avalon Interface

avs_DS1Wire_clk, //

avs_DS1Wire_chipselect, //

avs_DS1Wire_address, //

avs_DS1Wire_read, //

avs_DS1Wire_readdata, //

avs_DS1Wire_write, //

avs_DS1Wire_writedata, //

avs_DS1Wire_byteenable, //

avs_DS1Wire_reset, //

avs_DS1Wire_irq, //

avs_DS1Wire_export_DS1WireTX, //

avs_DS1Wire_export_DS1WireRxTX //

);

and some control registers where nios sets or resets some bits and assign them to registers like

// 1011

// interrupt enable register

//

reg EOWL; // enable OW low interrupt

reg EOWSH; // enable OW shorted interrupt

reg epd; // enable presence detect interrupt

//reg ias; // INTR active state

reg etbe; // enable transmit buffer empty interrupt

reg etmt; // enable transmit shift register empty int.

reg erbf; // enable receive buffer full interrupt

reg ersf; // enable receive shift register full int.

////wire [ 7: 0] INTEN_REG = {EOWL, EOWSH, ersf, erbf, etmt, etbe, ias, epd};

//wire [ 7: 0] INTEN_REG = {EOWL, EOWSH, ersf, erbf, etmt, etbe, 1'b0 , epd};

always @ ( posedge avs_DS1Wire_clk or posedge avs_DS1Wire_reset ) //

if ( avs_DS1Wire_reset ) //

begin

EOWL <= 1'b0;

EOWSH <= 1'b0;

ersf <= 1'b0;

erbf <= 1'b0;

etmt <= 1'b0;

etbe <= 1'b0;

// ias <= 1'b0;

epd <= 1'b0;

end

else

if ( avs_DS1Wire_chipselect && avs_DS1Wire_write && avs_DS1Wire_byteenable[0] && (avs_DS1Wire_address == 4'b1011) )

begin

EOWL <= avs_DS1Wire_writedata[7];

EOWSH <= avs_DS1Wire_writedata[6];

ersf <= avs_DS1Wire_writedata[5];

erbf <= avs_DS1Wire_writedata[4];

etmt <= avs_DS1Wire_writedata[3];

etbe <= avs_DS1Wire_writedata[2];

// ias <= avs_DS1Wire_writedata[1];

epd <= avs_DS1Wire_writedata[0];

end

alltogether looks pretty straight foreward what all the other files from maxim dallas did, ported to 32 bit nios world

the correct tcl (part of it, company related information removed) file for the component would be

# TCL File Generated by Component Editor 9.1sp1

# Fri Mar 05 15:43:04 CET 2010

# DO NOT MODIFY

# +-----------------------------------

# |

# | sopc_ds1wire_master "SOPC_DS1Wire_Master" v9.1

# | Michael Schmitt 2010.03.05.15:43:04

# | SOPC_DS1Wire_Master

# |

# | ./hdl/SOPC_DS1Wire_Master.v syn

# | ./SOPC_DS1Wire_Master.qip

# |

# +-----------------------------------

# +-----------------------------------

# | request TCL package from ACDS 9.1

# |

package require -exact sopc 9.1

# |

# +-----------------------------------

# +-----------------------------------

# | module sopc_ds1wire_master

# |

set_module_property DESCRIPTION SOPC_DS1Wire_Master

set_module_property NAME sopc_ds1wire_master

set_module_property VERSION 9.1

set_module_property INTERNAL false

set_module_property AUTHOR "Michael Schmitt"

set_module_property DISPLAY_NAME SOPC_DS1Wire_Master

set_module_property TOP_LEVEL_HDL_FILE hdl/SOPC_DS1Wire_Master.v

set_module_property TOP_LEVEL_HDL_MODULE SOPC_DS1Wire_Master

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL TRUE

# |

# +-----------------------------------

# +-----------------------------------

# | files

# |

add_file hdl/SOPC_DS1Wire_Master.v SYNTHESIS

add_file SOPC_DS1Wire_Master.qip SYNTHESIS

# |

# +-----------------------------------

# +-----------------------------------

# | connection point DS1Wire_clock

# |

add_interface DS1Wire_clock clock end

set_interface_property DS1Wire_clock ENABLED true

add_interface_port DS1Wire_clock avs_DS1Wire_clk clk Input 1

add_interface_port DS1Wire_clock avs_DS1Wire_reset reset Input 1

# |

# +-----------------------------------

# +-----------------------------------

# | connection point DS1Wire_export

# |

add_interface DS1Wire_export conduit end

set_interface_property DS1Wire_export ASSOCIATED_CLOCK DS1Wire_clock

set_interface_property DS1Wire_export ENABLED true

add_interface_port DS1Wire_export avs_DS1Wire_export_DS1WireRxTX export Bidir 1

add_interface_port DS1Wire_export avs_DS1Wire_export_DS1WireTX export Output 1

# |

# +-----------------------------------

# +-----------------------------------

# | connection point DS1Wire

# |

add_interface DS1Wire avalon end

set_interface_property DS1Wire addressAlignment DYNAMIC

set_interface_property DS1Wire associatedClock DS1Wire_clock

set_interface_property DS1Wire burstOnBurstBoundariesOnly false

set_interface_property DS1Wire explicitAddressSpan 0

set_interface_property DS1Wire holdTime 0

set_interface_property DS1Wire isMemoryDevice true

set_interface_property DS1Wire isNonVolatileStorage false

set_interface_property DS1Wire linewrapBursts false

set_interface_property DS1Wire maximumPendingReadTransactions 0

set_interface_property DS1Wire printableDevice false

set_interface_property DS1Wire readLatency 0

set_interface_property DS1Wire readWaitStates 0

set_interface_property DS1Wire readWaitTime 0

set_interface_property DS1Wire setupTime 0

set_interface_property DS1Wire timingUnits Cycles

set_interface_property DS1Wire writeWaitTime 0

set_interface_property DS1Wire ASSOCIATED_CLOCK DS1Wire_clock

set_interface_property DS1Wire ENABLED true

add_interface_port DS1Wire avs_DS1Wire_chipselect chipselect Input 1

add_interface_port DS1Wire avs_DS1Wire_address address Input 4

add_interface_port DS1Wire avs_DS1Wire_read read Input 1

add_interface_port DS1Wire avs_DS1Wire_write write Input 1

add_interface_port DS1Wire avs_DS1Wire_writedata writedata Input 32

add_interface_port DS1Wire avs_DS1Wire_byteenable byteenable Input 4

add_interface_port DS1Wire avs_DS1Wire_readdata readdata Output 32

# |

# +-----------------------------------

# +-----------------------------------

# | connection point DS1Wire_irq

# |

add_interface DS1Wire_irq interrupt end

set_interface_property DS1Wire_irq associatedAddressablePoint DS1Wire

set_interface_property DS1Wire_irq ASSOCIATED_CLOCK DS1Wire_clock

set_interface_property DS1Wire_irq ENABLED true

add_interface_port DS1Wire_irq avs_DS1Wire_irq irq Output 1

# |

# +-----------------------------------