ZBT/NoBL clock and PLL setup

I appreciate the reply. As it turns out, the Cyclone PLL's can't do external feedback anyway, so bringing the clock back in is pointless.

I just want to make sure I don't run into problems with excessive contention due to the clock at the RAM being significantly delayed from the clock in the FPGA. It's probably overkill, but I'd rather this board be reliable by design.

If it does turn into a problem, I could probably up the clock rate to 180, drop the core to 60, and insert NOP's between every command. A more intelligent design would check for contention before issuing the instruction, but then the latency becomes somewhat variable.

I'm rolling these boards on my own nickel, so a respin would come directly out of my pocket. ;)