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Am I making this too hard?
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Not really, being careful doesn't hurt.
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I'm using a TQFP package, and my trace lengths vary from 200mils to 2200mils, with the clock line straddling the middle at about 1000mil. If I loop the clock from the clock pin on the RAM back to a dedicated clock input, that would make the entire trace 2000mil, but the RAM would still see the clock at 1000 mil.
I'm not sure how to set this up. I would like the RAM to run at at least 160MHz (I'm using a 200MHz rated part, but the design needs to run at a minimum of 80MHz, with the dual-port interface running at 2X the system clock)
I haven't rolled the board yet but without seriously reworking it, it's going to be hard to get the trace lengths aligned. I may not even be able to do much better. As for the PLL, I know I need to bring in the mirror clock as a reference input, but beyond that, I'm not sure how to configure it to do what I need.
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1000 mil, longer or shorter, is about 155 ps skew, At 160 MHz you have 6,600 ps, so that shouldn't affect the timing budget much. At 2200 mil the total delay is about 390 ps or 5% of the clock period. Quartus II and TimeQuest will handle that nicely.
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I have the SRAM Clock routed out of PLL2_CLKOUTp. Right now, it's source terminated with a 50 ohm resistor, with a fairly straight shot to the clock input on the RAM.
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You can't use series termination if your signal goes to multiple destinations (unless you actually use special routing). So you need to parallel terminate at the FPGA. But there is no need to route the clock back to the FPGA as you can perfectly constrain everything using the output clock (and internally the PLL output feeding it).
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