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Altera_Forum
Honored Contributor
13 years agoI don't know about Xilinx - wouldn't touch it with a bargepole :)
I use a component in my VHDL code:
LIBRARY altera;
USE altera.altera_primitives_components.all;
....
odsda : opndrn
port map (
a_in => dp_SDaOut ,
a_out => Sda
) ; Don't know how to do this in Verilog - wouldn't touch that with a bargepole either :)