Altera_Forum
Honored Contributor
Honored ContributorXilinx FDCPE_1 Primitive
Does anyone know if Altera has a primitive similar to the FDCPE_1 (D Flip-Flop with Negative-Edge Clock, Clock Enable, and Async Reset)? Thanks!
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Altera_ForumHonored Contributor
Honored ContributorAre you doing a schematic or converting a X design? In schematic, just add a dffe and a not gate before the clock(or invert the clock at the source and give the output wire a usable name so many FFs can use it). If converting, I would write a behavioral one. Should only take a minute, and you can make sure the ports match exactly, rather than taking an Altera primitive and wrapping it.
