Honored ContributorHi,
I would like to design a x2 PCIE Gen 2.0 root port. In the system settings in Avalon MM Hard IP for PCIE, the option for number of lane is only x1 and x4. It says that if I will design x2 lane, I will select the x4 and do downtraning. What is meant by downtraining? Thanks Regdrs
Honored ContributorApparently, the term refers to PCIe link width determination during link training
PCIe spec says --- Quote Start --- The following are discovered and determined during the training process: �� Link width �� Link data rate �� Lane reversal �� polarity inversion --- Quote End ---Honored ContributorSorry, I did not understand. What is Link training? When does it happens?
Honored ContributorI'm wondering if study LTSSM operation can make you understand more?
