Writing to HPS memory from FPGA

Hi Kalimitas

After consulting a colleague , the example is able to work.

The HPS could read the values from OCR directly but you would need to make sure the data a sync between the FPGA and HPS before any side read or write the values.

There is this IP called cache coherency translator that could be used to accessed the OCR and it will maintain the coherency between both sides.

Unfortunately the IP is not available for Cyclone V.

However you could read the OCR through the Accelerated Coherency Port for Cyclone V

There is no reference design for accessing the ACP, but you could refer to the document below on the signals required and its description.

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/accelerator-coherency-port.html

Regards

Jingyang, Teh

One way is to

Regards

Jingyang, Teh