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Hi,
well here are some answers to your questions...
ad 1) the recommendation in the handbook is to connect all unused Pins to ground in Hardware and turn the same Option on in the Quartus Software. This "simulates" the device would have more ground Pins resulting in better current Distribution (more Pins). I always left These Pins open in HW and turned the "tri-state with weak pull up" Option in Quartus. If you connect unused Pins to gorund in Hardware be sure to match HW with the programming file to prevent any Pin driving a Signal in your Programm code while being connected to HW...
ad 2) any clock line like any Signal line as well is an antenna and may - if left "open" - cause voltage overshoot or undershoot due to Reflexion. If you manage to match clock line impedance (length and Routing of trace on pcb) and clk frequency this may result in voltage Level exceeding the specification reducing the life time of your FPGA. To prevent this you should either provide a footprint for a pull or series resistor (or take care of the Routing / measure the Signal in real HW to check if there are any exceeding over-/undershoots)
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I synthesized the design with the pin placement just now. I have taken a look at the generated .PIN file. For all the normal unused I/O it says it will use "reserved input with weak pull up". In one of the app notes I read that if DEV_CLRn and DEV_OEn are unconnected they should be tied to ground. In the .PIN file they are however of the type reserved input with weak pull up. Isn't there going to be running a small current now?
For my unused CLK inputs it says they are of the type "GND+". These include the unused CLK inputs on the expansion header, because currently I am not using these. The .PIN file describes the type "GND+" should be connected to GND. But it can also be connected to a valid signal on the board. I guess this means the CLK inputs should not be left floating. I suppose I can connect the CLK pins that are not used for my expansion header directly to ground (so not with a resistor in series)?
I suppose that if the CLK inputs are unused on the I/O header I should provide a PULL DOWN resistor to ground on those lines? I guess I can use one resistor to provide the PULL DOWN for both the CLK inputs on my expansion header?
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ad 3) Neither JTAG nor EPCS4 configuration require an on board oscillator. JTAG uses the JTAG "TCK" clock Signal while the DCLK Signal for the EPCS4 configuration Interface is generated by the FPGA itself. Any design w/o dedicated clock can only be combinatorical logic, but the FPGA can be programmed and operated w/o external oscillator
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Allright, just as I thought. This is completely clear now to me.
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ad 4) I would argue using pull resistors is mainly to provide a stable Signal on the line during the configuration cycle (FPGA Pins tristate) and provide a known load to stabilize signals (over- undershoot issue like for 2) question).
Hope that helps a Little :-)
Carlhermann
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I will leave these away for the time being. I can always hand solder some pull ups and correct the design afterwards.
Honored Contributor
