Workaround for wrongly assigned DQS pin for DDR SDRAM controller in Cyclone IV FPGAs

Thanks for sharing and glad that you found a work around for your system. Regarding checking your solution fully, my suggestion is to create a test system with your modified controller and the Avalon-MM Traffic Generator and BIST Engine, and keep it running across the temperature range, watching the status bits somehow (SignalTap, probes, custom logic, etc.).

As some additional information: what I ran into while modifying the ALTMEMPHY to work with LPDDR was that the primary statement in the generated files which causes the fitter to complain about the DQ/DQS signals is the embedded DQ_GROUP clause within phy_alt_mem_phy.v (search for DQ_GROUP). This attribute statement causes the fitter to enforce the pin placement and I/O standard to match it's expected values/rules. Without that statement, the fitter no longer performs those checks and presumably there is some (negative) trade-off for not using the DQ/DQS group, but certainly at low performance points (I have gone up to 150MHz) the resulting system works fine.