will Cyclone III work with unconected VCCA PLL ??

I connected VCCD1 pin (second pin I didn't connected) and PLL1 is working.

i soldered all board and here is picture of my DIY cyclone III prototype board :)

https://www.alteraforum.com/forum/attachment.php?attachmentid=331

Cool PCB design

I guess PLL power diff from Cyclone2 may solve some power issue in Cyclone3. So they div VCC to 2 or more.

I just found out why PLL is working improperly and instead of 16Mhz give out 22Khz its because I also forgot to connect VCCD1;2 pins to 1,2V core voltage.

I will have to correct that mistake, and then PLL must work properly.

I made today some tests and found strange PLL behavior it outputs strange frequency in place of 16Mhz I get 22,7Khz frequency I set PLL to ratio 1/1 so it need to be 16Mhz, I tested it by making such test code where i created 2 clocks one direct 16Mhz clock input I routed to Global clock line and other was PLL clock and for testing I created logic 6bit(/128) frequency divider.

and as I have only 1Msps oscilloscope I saw that output of non PLL clock logic was 128Khz and it is correct, value for 16Mhz clock, but PLL clock I measured directly and it was 22,7Khz :(

Why PLL don't work correctly ??

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--  Entity Declaration
ENTITY Cyclone_III_pin_test IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		A : Out STD_LOGIC_vector(7 downto 0);
		Clk : IN STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END Cyclone_III_pin_test;
Architecture Cyclone_test of Cyclone_III_pin_test is 
signal CLK_1ms,B,B2,C,D: std_Logic;
signal Q,Q2 : STD_logic_vector (5 downto 0);
component C3PLL_test
	PORT
	(
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
end component;
component clk_route
	PORT
	(
		inclk		: IN STD_LOGIC ;
		outclk		: OUT STD_LOGIC 
	);
end component;
begin
clk_16M : clk_route 
Port map( inclk=>clk,outclk=>C);
CLock_PLL : C3PLL_test 
Port map( inclk0=>clk,c0=>CLK_1ms);
--CLK_1ms<= CLK;
A(3) <= CLK_1ms;
A(2) <= CLK;
A(1) <= C;
A(0) <= CLK_1ms;
A(4)<= D;
process(clk_1ms)
begin 
--if clk_1ms ='1' then
	if rising_edge(clk_1ms) then
	Q<=Q+1;
		if Q ="000000" then 
			if B='1' then
			A(7 downto 5)<= "111";
			B<='0';
			else A(7 downto 5)<= "000"; B<='1';
end if;
end if;
end if;
end process;
process(c)
begin 
--if clk_1ms ='1' then
	if rising_edge(c) then
	Q2<=Q2+1;
		if Q2 ="000000" then 
			if B2='1' then
			D<= '1';
			B2<='0';
			else D<='0'; B2<='1';
end if;
end if;
end if;
end process;
end Cyclone_test;

here is picture how I connected second VCCA2 pin.

I just need to isolate it with read silicon isolator and board is ready for tests :)

https://www.alteraforum.com/forum/attachment.php?attachmentid=322

it is my DIY cheap 2 layer board trace width 0.25mm Via hole 0.4mm board cost me 38$ so it is not big money loose, and here is pictures of board with connected VCCA1 pin

https://www.alteraforum.com/forum/attachment.php?attachmentid=319

here is picture of second PCB where I made first drilling test to see if it is possible to drill such hole and gain some drilling experience :)

https://www.alteraforum.com/forum/attachment.php?attachmentid=321

https://www.alteraforum.com/forum/attachment.php?attachmentid=320

in 2 layers I managed to route first 2 ball rows + configuration pins for Fast Passive Parallel configuration with MAX3000 and 16Mb parallel flash, the main purpose of this board was to evaluate this new super fast +cheep (totally 5$) configuration scheme :)

and in addition I have 50 IOs and I can add external voltage to 4 IO banks, by external power supply(or connect to 3.2V on board regulator), that kind of feature is not supported on any altera Dev.kit, So I have 4 individual IO banks that can by set at any voltage I need :)

I choose to use BGA256 package because 144pin package had too small IO count(94), my previous cyclone II had 208 pin package (it was enough), so cyclone III I had only one choice BGA256, where for first 2 rows I can route 124IOs that is by 30IOs more than 144pack :)

so 124 is reasonable IO count for connecting some high count devices, ofcourse by data sheet BGA256 pack has 182 IOs, but then I need to make 4 layer PCB which cost about 200$ it is too much for hobby staff, and to get it cheap you must make more than 100 boards and then sell them.

Hello,

who ever experienced Cyclone II PLL problems due to SSO effects knows that the internal PLL supply regulator introduced with Cyclone III is an important improvement. It can be reason enough to start a redesign. When you read the manual thoroughly, there should be no doubt how to connect power supplies. Reference or evaluation board designs are usually a good starting point for a new design.

I think, most confusion with Cyclone III "unexpected innovations" has arised for developers experienced to Cyclone II. They thought to know how to migrate but didn't read the manual exactly. E. g. when migrating an existing design, just change the pin assignments in CAD part and in Quartus. This ends up in an almost functional design - except for VCCA connected to 1V2.

I can't see from Epis' board photo if it's a just a homemade evaluation board or if the design serves a purpose that can't be satisfied by an evaluation tool. To my opinion, 10 mils PCB technology is somewhat coarse, but it may work for low to medium pin count designs. Possible SI qualities can't be judged without seeing the backside.

Regards,

Frank

VCCA is required for a Cyclone III class product because:

1. It's a 65nm product. Smaller process geometries require more technical discipline with respect to voltage (affects the IC designer and the board designer equally).

2. The Cyclone III PLLs are far more sophisticated than Cyclone II. In order to keep the PLL jitter superior to alternative clock sources on a board, it needs its own, clean power source.

For future reference, you can just take the schematics from the starter kits:

http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html#documentation

and save yourself a lot of headaches experimenting with what Altera means by the word "required".

Out of curiosity, did you spend more than $200 in your time and money to build this home baked board?

GG

I made some simple logic which routs clock signal to output pin, I have on board 16mhz clock and I got much lower frequency clock signal about 1Mhz, and I changed PLL clock presscaler and got different results so I must say that chip don't work stable with one VCCA1 pin connected and other VCCA2 unconnected.

but at least it configures :)

also I noticed that I cant see clock signal on output pins without using PLL by directly connecting clock signal to internal logic clock signal(I had 16bit counter for clock division), and there was no signal output pin, also tried to rout clock signal in global line and still no results, I had results just with using PLL.

so I guess I will have to drill one more hole and solder VCCA2 pin :(

Hello,

manual specification is clear in this respect:

--- Quote Start ---

All VCCA pins must be powered to 2.5-V (even when PLLs are not used), and must be powered-up and powered-down at the same time.

--- Quote End ---

The same is stated in the Pinout document. Please don't ask what happens, if you ignore it. Did you see configuration functional with only VCCA1 connected?

Regards,

Frank