Honored Contributor
Honored ContributorTwo more difficult problems about this implementation were found yesterday... :cry:
1). Although the SDI receiver works, I found that the data of video frame in DDR3 are all 0x00, which means nothing is transferred by SGDMA. If the SGDMA transfer is correct, I should see two blocks of data in DDR3. One is an Avalon-ST control packet which indicates the format of coming video such as resolution. The other is an Avalon-ST video packet which contains frame or field data. Now the problem is that I can see correct control packet data in DDR3 but the video packet data in DDR3 are all zero. I'm trying to observe the waveform in Modelsim to make sure there's a valid Avalon-ST video packet as an input of SGDMA. Does any wrong parameter setting cause this problem??? 2). Because SGDMA cannot give me a good result, I try to use Frame Buffer IP as Socrates's suggestion. The FPGA design is as follows: (SDI Rx-->CVI-->Frame Buffer-->DDR3) After I enable the GO bit in the control register of Frame Buffer, the data in DDR3 are changed . (The initial data in DDR3 has been set to zero in my program in order to see the data change) However, the data are not what I expect. (The data should be the YCbYCr data from a color bar test pattern video source) I'm wondering whether I accessed incorrect address in DDR3 so that the data is wrong. The base address in the Frame Buffer setting is 0x00000000. Does this address represent a zero address offset of the first frame buffer in DDR3? Moreover, how to compute the starting address of the second frame buffer and even third frame buffer in DDR3? Thank you. :)
