Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi Socrates
Thank you for your reply. I'll try to use frame buffer IP tomorrow. In fact, I do not understand why a continuous stream and burst transfers cause me this problem. Does a continuous stream lead to a full FIFO in SGDMA and affect the SDI receiver? I'm grateful if you are willing to explain it more. BTW, in my working project of SGDMA, the input video source comes from an Altera test pattern generator IP and is feed to SGDMA. (TPG-->(some avalon-st adapter and DC FIFO)-->SGDMA) I don't see much difference between this working project and the SDI one we discussed. (SDI Rx-->CVI-->(some avalon-st adapter and DC FIFO)-->SGDMA) The video sources are both in Avalon streaming interface. I am also wondering what the difference between these two designs. Sorry for asking you too many questions. I'm just very curious about the reasons. Thanks.